What is Field Effect Transistors ( FETs )

Definition of FET:

A field-effect transistor (FET) is a type of transistor commonly used for weak-signal amplification (for eg, for amplifying wireless signals). The device can amplify analog or digital signals. It can also switch DC or function as an oscillator.

Explanation of Field effect transistor:

The field-effect transistor (FET) is a three-terminal device used for a variety of applications that match, to a large extent, those of the BJT transistor . Although there are important differences between the two types of devices, there are also many similarities that will be pointed out in the sections to follow.The primary difference between the two types of transistors is the fact that the BJT transistor is a current-controlled device as depicted , while the JFET transistor is a voltage-controlled device. In other words, the current IC is a direct function of the level of IB. For the FET the current I will be a function of the voltage VGS applied to the input circuit.In each case the current of the output circuit is being controlled by a parameter of the input circuit—in one case a current level and in the other an applied voltage.

Just as there are npn and pnp bipolar transistors, there are n-channel and p-channel field-effect transistors. However, it is important to keep in mind that the BJT transistor is a bipolar device—the prefix bi- revealing that the conduction level is a function of two charge carriers, electrons and holes. The FET is a unipolar device

Depending solely on either electron (n-channel) or hole (p-channel) conduction. The term field-effect in the chosen name deserves some explanation. We are all familiar with the ability of a permanent magnet to draw metal filings to the magnet without the need for actual contact. The magnetic field of the permanent magnet has enveloped the filings and attracted them to the magnet through an effort on the part of the magnetic flux lines to be as short as possible. For the FET an electric field is established by the charges present that will control the conduction path of the output circuit without the need for direct contact between the controlling and controlled quantities. There is a natural tendency when introducing a second device with a range of applications similar to one already introduced to compare some of the general characteristics of one versus the other. One of the most important characteristics of the FET is its high input impedance. At a level of 1 to several hundred megohms it far exceeds the typical input resistance levels of the BJT transistor configurations—a very important characteristic in the design of linear ac amplifier systems. On the other hand,the BJT transistor has a much higher sensitivity to changes in the applied signal. In other words, the variation in output current is typically a great deal more for BJTs than FETs for the same change in applied voltage. For this reason, typical ac voltage gains for BJT amplifiers are a great deal more than for FETs. In general, FETs are more temperature stable than BJTs, and FETs are usually smaller in construction than BJTs, making them particularly useful in integrated-circuit (IC) chips. The construction characteristics of some FETs, however, can make them more sensitive to handling than BJTs.

Types of FET:

Junction field-effect transistor (JFET)

Metal-oxide-semiconductor field-effect transistor (MOSFET).

The MOSFET category is further broken down into depletion and enhancement types, which are both described. The MOSFET transistor has become one of the most important devices used in the design and construction of integrated circuits for digital computers. Its thermal stability and other general characteristics make it extremely popular in computer circuit design.

Construction and Characteristics of JFET:

JFET is a three-terminal device with one terminal capable of controlling the current between the other two. In our discussion of the BJT transistor the npn transistor was employed through the major part of the analysis and design sections, with a section devoted to the impact of using a pnp transistor. For the JFET transistor the n-channel device will appear as the prominent device, with paragraphs and sections devoted to the impact of using a p-channel JFET. The basic construction of the n-channel JFET. Note that the major part of the structure is the n-type material that forms the channel between the embedded layers of p-type material.

The top of the n-type channel is connected through an ohmic contact to a terminal referred to as the drain (D), while the lower end of the same material is connected through an ohmic contact to a terminal referred to as the source (S). The two p-type materials are connected together and to the gate (G) terminal. In essence, therefore, the drain and source are connected to the ends of the n-type channel and the gate to the two layers of p-type material. In the absence of any applied potentials the JFET has two p-n junctions under no-bias conditions. The result is a depletion region at each junction that resembles the same region of a diode under no-bias conditions. Recall also that a depletion region is that region void of free carriers and therefore unable to support conduction through the region.

VGS = 0 V, VDS Some Positive Value :

A positive voltage VDS has been applied across the channel and the gate has been connected directly to the source to establish the condition VGS = 0 V. The result is a gate and source terminal at the same potential and a depletion region in the low end of each p-material similar to the distribution of the no-bias conditions. The instant the voltage VDD ( VDS) is applied, the electrons will be drawn to the drain terminal, establishing the conventional current ID with the defined direction. The path of charge flow clearly reveals that the drain and source currents are equivalent (ID = IS). Under the conditions appearing, the flow of charge is relatively uninhibited and limited solely by the resistance of the n-channel between drain and source.

It is important to note that the depletion region is wider near the top of both p-type materials. Assuming a uniform resistance in the n-channel, the resistance of the channel can be broken down to the divisions appearing. The current ID will establish the voltage levels through the channel as indicated on the same figure. The result is that the upper region of the p-type material will be reverse biased by about 1.5 V, with the lower region only reverse-biased by 0.5 V. Recall from the discussion of the diode operation that the greater the applied reverse bias, the wider the depletion region—hence the distribution of the depletion region.

The fact that the p-n junction is reverse-biased for the length of the channel results in a gate current of zero amperes as shown in the same figure. The fact that IG = 0 A is an important characteristic of the JFET.As the voltage VDS is increased from 0 to a few volts, the current will increase as determined by Ohm’s law and the plot of ID versus VDS will appear. The relative straightness of the plot reveals that for the region of low values of VDS, the resistance is essentially constant. As VDS increases and approaches a level referred to as VP, the depletion regions will widen, causing a noticeable reduction in the channel width. The reduced path of conduction causes the resistance to increase and the curve in the graph to occur. The more horizontal the curve, the higher the resistance, suggesting that the resistance is approaching “infinite” ohms in the horizontal region. If VDS is increased to a level where it appears that the two depletion regions would “touch”, a condition referred to as pinch-off will result. The level of VDS that establishes this condition is referred to as the pinch-off voltage and is denoted by VP In actuality, the term pinch-off is a misnomer in that it suggests the current ID is pinched off and drops to 0. However, this is hardly the case—ID maintains a saturation level defined as IDSS. In reality a very small channel still exists, with a current of very high density. The fact that ID does not drop off at pinch-off and maintains the saturation level indicated is verified by the following fact: The absence of a drain current would remove the possibility of different potential levels through the n-channel material to establish the varying levels of reverse bias along the p-n junction. The result would be a loss of the depletion region distribution that caused pinch-off in the first place.

As VDS is increased beyond VP, the region of close encounter between the two depletion regions will increase in length along the channel, but the level of ID remains essentially the same. In essence, therefore, once VDS = VP the JFET has the characteristics of a current source.The current is fixed at ID = IDSS,but the voltage VDS (for levels VP) is determined by the applied load.The choice of notation IDSS is derived from the fact that it is the Drain-to-Source current with a Short-circuit connection from gate to source. As we continue to investigate the characteristics of the device we will find that:IDSS is the maximum drain current for a JFET and is defined by the conditions VGS = 0 V and VDS = |VP|.

VGS < 0 V :

The voltage from gate to source, denoted VGS , is the controlling voltage of the JFET.

Just as various curves for IC versus VCE were established for different levels of IB for the BJT transistor, curves of ID versus VDS for various levels of VGS can be developed for the JFET. For the n-channel device the controlling voltage VGS is made more and more negative from its VGS = 0 V level. In other words, the gate terminal will be set at lower and lower potential levels as compared to the source. A negative voltage of 1 V has been applied between the gate and source terminals for a low level of VDS.The effect of the applied negative-bias VGS is to establish depletion regions similar to those obtained with VGS = 0 V but at lower levels of VDS. Therefore, the result of applying a negative bias to the gate is to reach the saturation level at a lower level of VDS for VGS = 1 V.The resulting saturation level for ID has been reduced and in fact will continue to decrease as VGS is made more and more negative.

Note how the pinchoff voltage continues to drop in a parabolic manner as VGS becomes more and more negative. Eventually, VGS when VGS = VP will be sufficiently negative to establish a saturation level that is essentially 0 mA, and for all practical purposes the device has been “turned off.”The level of VGS that results in ID = 0 mA is defined by VGS = VP, with VP being a negative voltage for n-channel devices and a positive voltage for p-channel JFETs.

On most specification sheets the pinch-off voltage is specified as VGS(off) rather than VP. A specification sheet will be reviewed later in the chapter when the primary elements of concern have been introduced. The region to the right of the pinch-off locus is the region typically employed in linear amplifiers (amplifiers with minimum distortion of the applied signal) and is commonly referred to as the constant-current, saturation, or linear amplification region.

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